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mdct.tar
- 这是06年4月刚刚完成的程序,从opencore.org下载而来。用vhdl语言描写,以及matlab仿真,testbench,以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distribut
color_converter.tar
- 此代码实现不同图像颜色制式之间的相互转换,如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换,包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件,相信对大家有一定的帮助
DCT
- altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim 验证,文件中包含TESTBENCH ,直接可用
vrt
- Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
GUI_Matting
- matlab编写的交互式image matting程序,包括:Poisson,Hillman,Ruzon等方法和源图像-matlab interactive image matting procedures, including: Poisson, Hillman, Ruzon methods and sources image
testbench
- 我刚学了matlab小程序,觉得很适合初学者。-matlab small programs, suitable for beginners.
VR
- 用于进行变量降维的matlab程序,大家可以试一试,很有效哟-Variable Reduction Testbench MATLAB modules,it is very effective, we can try, very effective ..............
FIR
- 14阶FIR滤波器的硬件实现,附加testbench与Matlab验证.-a FIR with 14 taps, packed with testbench and matlab verification
fibonacci_matlab_verilog
- 使用Matlab和Verilog实现fibonacci序列,包括源代码和testbench-use matlab and verilog to realize fibonacci sequence,including source code and testbench
FIR_matlab
- 使用matlab的fdatool工具生成的VerilogFIR滤波器代码,自带测试testbench-The the Matlab fdatool tool to generate VerilogFIR filter code, self-testing testbench
matlab-and-verilog-fir4_3
- 四抽头FIR滤波器matlab,verilog顶层,子模块,以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
3-ddc-cic_5hb_firmatlab-testbench)
- 三通道上下变频cic_5hb_firmatlab仿真程序-Three-channel down conversion cic hb fir matlab simulation program
firfilterPfpga
- FIR滤波器的仿真,使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件,并产生testbench文件进行仿真。-FIR filter verilog coe testbench
ADC_Data_Recv_Module
- 接收机测试输入信号, 生成正余弦波,采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
Clock_Synchronization_Module
- 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
FFT_Module
- 接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)
Orthogonization_Module
- 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
CIC_Filter_Module
- 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)